1. Field
The present invention relates generally to integrated circuits, and more specifically to techniques for strapping a primary conductor with a secondary conductor to provide electrical connectivity as an alternative for the primary conductor.
2. Background
With modern advances in integrated circuit (IC) process technology, it is now possible to fabricate radio frequency integrated circuits (RFICs) for various applications such as wireless communication, networking, computing, and so on. These RFICs may include various analog circuit blocks (e.g., filters) that conventionally are implemented using bulky discrete components. By implementing analog circuit blocks on RFICs, various benefits may be obtained such as smaller size, lower cost, improved reliability, and so on.
The performance of analog circuit blocks (e.g., filters) fabricated on an RFIC is dependent on the electrical characteristics of the materials used to form circuit elements (e.g., inductors) that make up the circuit blocks. For example, the RF performance of inductors and transmission lines is dependent on the resistive loss of the metal conductor used to form these circuit elements. Many RFIC fabrication processes use aluminum or aluminum alloy, which is a relatively lossy material, and relatively thin thickness (e.g., 0.5–3 μm) for the metal layers. This then results in relatively high resistive loss for the metal conductor, which in turn limits the quality factor (Q) that may be achieved for inductors. Consequently, it is not possible to fabricate high-Q circuits with this lossy metal conductor.
Thick copper conductor, which is a low-loss metal, is a new development in RFIC processes. Because of its thick size (which may be 10 micrometer (μm) thick) and the higher conductivity of copper, low resistive losses can be achieved for the thick copper conductor. This then improves the RF performance of some circuit elements such as planar inductors and transmission lines. In particular, with the low resistive loss of thick copper conductor, quality factors on the order of 25 or greater may be attained for inductors at cellular and PCS frequencies. This enhanced performance is achieved without the need for expensive fabrication processing stages such as those encountered in Micro-Electro-Mechanical systems (MEMs) technologies. New possibilities in RFIC development can now be realized, such as on-chip integration of resonator tanks for voltage controlled oscillators (VCOs), high-Q passive filtering, low-loss interconnection of on-chip circuit blocks, and so on.
The fabrication process for RFICs is complicated and typically includes many processing steps. For example, circuit elements are often fabricated and interconnected with a series of wafer processing steps (e.g., etch and deposition steps). The thick copper metal, if used for the RFICs, is then formed by metal deposition, which is normally done after the wafer processing and is referred to as post-processing. For some IC fabrication processes, the wafer processing and metal deposition are performed at different facilities using different equipment.
For many IC fabrication processes, long lead times are associated with manufacturing of RFICs that use low-loss metal. The lead times may be further increased if basic testing, such as direct current (DC) testing, cannot be performed on RFICs before the low-loss metal is deposited. In particular, some circuit elements such as inductors are formed by the low-loss metal and would not be present on the RFIC until the low-loss metal has been deposited. Circuit elements relying on these inductors for interconnection would then be opened (i.e., not electrically connected) until then. It would thus not be possible to perform DC testing on these RFICs until the low-loss metal has been deposited.
The delay in the DC testing caused by the low-loss metal extends manufacturing time and further increases costs. These problems are exacerbated if the wafer fabrication and DC testing are performed in one facility and the metal deposition is performed at another facility. In this case, additional delays and costs are incurred to ship the RFICs from one facility to another, and then back to the same facility for DC testing.
There is therefore a need in the art for techniques to interconnect circuit elements in RFICs using alternative means for primary conductors that are to be formed subsequently.